资源列表
Q22-c.tar
- hdl design using verilog for beginer
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
ALU ALU
- Codigo para un sumador en verilog
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
Vivado_2037
- vivado 2015.4 lisence
AD5683 Driver
- AD5683 16位高精度DAC的FPGA程序，采用Verilog语言编写(AD5683 16 bit high precision DAC FPGA program, written in Verilog language)
zutil.h
- for everybody to understsn the file
crc_nguyenquanicd
- design crc module in data network transmission
D_cache
- 数据缓存的模块设计，连接流水线mem模块。(The module of data cache is designed to connect the pipeline MEM module.)
COUNT
- 本程序是基于verilog语言的程序，作用是计数器，数码管显示.(This procedure is based on Verilog language program, the role is to eliminate keyboard shaking, digital display.)
vhdl
- 用VHDL语言实现CD4527（BCD比例乘法器）仿真(The simulation of CD4527(BCD proportional multiplier))
8815397fft
- 基于MATLAB/FPGA的fft的verilog实现。(Verilog implementation of FFT based on MATLAB/FPGA)