资源列表
ILI9163-C-code
- Ilitek 9163 Initilization code using C Language
MSP430F552x_uscia0_spi_09
- TI msp430f5529,向SPI口(master)写数据-USCI_A0, SPI 3-Wire Master Incremented Data, TI msp430f5529
C51
- 基于5-1单片机环境噪声测量仪的设计，包含主程序、中断服务程序、显示程序、(Based on 51 single-chip environmental noise detector proteus simulation file containing a set of project files noise.dsn Keil main code main.c 6 relevant articles and graduation thesis design through simulation)
mux16
- 基于quartus的FPGA乘法器Verilog程序(FPGA multiplier program based on quartus)
UC1676C
- 51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)
apb_uart
- 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
Verilog HDL
- 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)
adc_cfg
- adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)
RS232
- 串口收发代码，可设置速率，工程中已验证可用(Serial transceiver code, can set the rate, the project has been verified to be available)
AHB-task-slave-master
- ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)
模24计数器
- 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)