资源列表
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
UART
- UART verlog 源码-UART verlog.......................
4945579081DCT_2D
- dct-20 verilog vhdl de2
top_module
- OFDM Gaurd Detector, Symbol length = 1024 & Gaurad Length = 256, and test bench written in verilog!
BT656_RGB
- BT656转RGB的算法实现代码，使用VORILOG语言编写-BT656-->RGB, verilog
decode_64_66
- 自编的64B/66B解码程序，做毕业设计的时候写的。-The decoding process 64B/66B , written when i am in the school。
encode_64_66
- 自编的64B/66B编码程序，下次上传解码程序。-the 64B/66B coding process is written by myself, i will upload the decoding process next time.
digital_voltage
- VHDL开发的数字电压表，量程5V，精度0.01V，在Sparten3E FPGA运行通过-VHDL development of digital voltmeter, range 5V, precision 0.01V, running through the Sparten3E FPGA
Frame-synchronizer-
- 原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。-Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine sync
Bit_synchronization
- 这是一个位同步的FPGA完整代码，是用Verilog写的，其中包括分频、时钟、时钟提取等各模块以及顶层文件，做调制解调的朋友可以-This is a synchronous FPGA complete code is written in Verilog, including frequency, clock, clock extraction module and the top-level file, do the modulation and demodulation of a frien