资源列表
latch
- 门拴电路,4位选择器，alu,用verilog写的。-doors Shuan circuit, four selectors, ALU, with Verilog writes.
DSP281x_PieCtrl
- TI公司的281x的pie中断源码,大家可以看看!-TI's 281x interrupted the pie source, we can see!
add_1p
- 数字信号处理的fpga实现，用VHDL编程设计加法器-Digital signal processing to achieve the FPGA with VHDL Programming adder
motor
- 这是一段控制步进电机转动的代码。希望对搞电机的同行有所帮助。驱动芯片是297+298-this is a code for controlling the step motor.
test4
- 用 vhdl 语言实现的 32个 条目的 ARP-using vhdl language to realize ARP protocol with 32 entries
shizhongyuan
- 电子钟具有显示年、月、日、时、分、秒及星期功能-Display Electronic clock with year, month, day, hour, minute, second and week functions
volume
- dsp 卷积算法原理代码 观察卷积运算后的波形-dsp code convolution algorithm principle observed waveform after convolution
VIDEO_AD_8V
- SC9766视频采集芯片，双通道，工作频率25M。-sc9766 verilog
viterbia
- 实现viterbi译码，通过比较最小汉明距来判别最佳路径，删除不必要的路径，最终找到最佳路径。-Implement viterbi decoding, by comparing the minimum hamming distance to distinguish the best path, delete unnecessary path, finally find the best path.
IFCtrl.v
- dlx design的if模块，instruction fetch，stage 1-dlx design of if module, instruction fetch, stage 1
main
- msp430模拟量采集数码管显示，电压电阻电流-Msp430 analog acquisition of digital tube display, voltage resistance current
msp430-8k-sample
- *********************************************** *文件名：VoiceSample语音的采集与回放 *描述：ADC10采样方式为单通道单次采样，定时器A0触发方式采样，A0的频率为8K，所以采样频率为8K * P1.6控制DAC0832的CS, P1.7控制DAC0832的WR, P2与DAC0832数据口相连接,430通过 * P1.1口采样数据 *版本号：v1 *作者：hongdanyang **********