资源列表
butterfly
- 蝶形运算的VHDL代码，可以实现，没验证-VHDL code butterfly operations can be achieved, no authentication
sdmlstruct
- This code implements the structural modelling of mealy type sequence detector to detect the sequence 1010. The code is a quartus project file
DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
vlsiram
- VHDL RAM 16 * 8 source code FPGA
gcd
- 求最大公约数的vhdl 源代码 gcd-gcd
dpll
- dpll is used to lock the data
clk
- 这是一个数字秒表的设计。几时周期为0.01s-1h。带有计数器的清零端，还有一个秒表的计时起止控制开关，最后计时信息显示在数码管上。-This is a digital stopwatch design. When a period of 0.01s-1h. Cleared with the end of the counter, and a stopwatch start and end time-control switch, the last time the information di
PWM
- PWMc语言代码，产生PWM波形，用于各种产品以及测试-PWMc language code to generate PWM waveforms for a variety of products and test
autosell_newspaper
- 這是FPGA自動販賣機的功能,名字為autosell_newspaper.rar,其中使用了有限狀態機。-FPGA vending machines function, the name of the autosell_newspaper.rar, which uses the finite state machine.
signal
- 数字信号处理，节约函数，FFT变换，快速傅立叶变换 -Digital signal processing, saving function, FFT, fast Fourier transform
EEPROM
- AT24C02是256Byte存储容量的EEPROM，内部 寻址时，要用32个页地址，每页有8Byte-AT24C02 is 256 byte block storage capacity of EEPROM, internal When addressing, want to address with 32 pages, each page 8 byte
BY_TEST4
- 用485信号测试通讯线正反，已经过测试,用于工业通信线开路建成-used 485 test line true or false