资源列表
64位乘法器
- 基于fpga的64位乘法器的实现，基于Verilog(Implementation of 64-bit multiplier based on FPGA)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
PID_Verilog
- PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
adc_data_receive
- adc器件ads62p49模数转换代码，已在工程中验证可用(ADC device ads62p49 analog-to-digital conversion code has been validated in Engineering)
LFM
- 该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
SPI_ADC
- spi串行输出ADC——AD7989的verilog源代码。(Spi serial output ADC - AD7989 Verilog source code.)
bt656_decode
- 将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
Xilinx
- 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MA
polyPhaseFilter
- 数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)
CDCM6208_SPI
- 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
PID
- 利用Verilog语言实现PID增量式控制，输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)
sram_ctr
- SRAM VERILOG 实现FPGA控制SRAM的功能。测试可以使用。(SRAM verilog fpga vivado ise quartus.)