资源列表
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
half_adder
- half adder with testbench
jishuqi
- 各式计数器代码，从十五到六的各式计数器，方便大家参考，一看多用-Counter all kinds of code, from 15 to six kinds of counters to facilitate reference, see more ~ ~ ~
LPC1752DAC
- 单片机1752 数字量~模拟量转换程序,实现数字量~模拟量转换.-MCU 1752 digital- analog conversion, digital- analog conversion.
mqst
- 用Verilog HDL编程实现曼切斯特编码器的功能，程序结构简单，仿真后波形延时这方面也进行了相关的优化-verilog HDL
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
C8051F120-IO
- C8051F120 IO口控制输入输出函数，运行成功。大家可以直接调用此函数，进行IO口设置。-C8051F120 IO port to control input and output functions, running successfully. We can call this function directly for IO port settings.
URAT-code
- 使用Verilog HDL语言编写的URAT接口代码，实现串行数据传输功能-UART of Verilog HDL code to realize serial communication functio by Simon of Shenzhen University.
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
GPS-jiegoutidef
- 包含如下： struct GPSGPRMC //0183协议数据 struct GPSGPGGA //0183协议数据
coordinate-transformation
- 实现坐标变换，包括clark和park变换，clark变换实现三相静止坐标转换到两相静止坐标，park变换实现两相静止坐标转换到两相旋转坐标-Achieve coordinate transformation, including clark and park transform, clarke transform phase static coordinate conversion to the two-phase stationary coordinate, park transform t
pinlv
- 频率计单片机实现，超过10000hz报警。可以用protues仿真。-MCU frequency meter, more than 10000hz alarm. You can use proteus simulation.