资源列表
计数器：generate语句的应用
- VHDL语言应用实例,计数器的设计,用GENERATE语句实现-VHDL example, counter design, realization GENERATE statement
pulse
- 利用分频可以产生一系列脉冲，根据输入脉冲的不同决定你得到的一系列脉冲频率
clr_m
- 用FPGA实现的模糊控制器 部分用VHDL编写的源程序
delay.rar
- 用vhdl的状态机实现精确的1us的延时程序,VHDL state machine used to achieve precise 1us delay procedures
traffic
- 实现交通灯的vhdl程序，可在quartus里运行，这是一个平时实验课中场遇到的小程序。-Vhdl traffic lights to achieve the program can be run in quartus, this is a normally encountered in the experimental class midfielder applet.
fenpinqi
- 偶数倍分频：偶数倍分频应该是大家都比较熟悉的分频，通过计数器计数是完全可以实现的。如进行N倍偶数分频，那么可以通过由待分频的时钟触发计数器计数，当计数器从0计数到N/2-1时，输出时钟进行翻转，并给计数器一个复位信号，使得下一个时钟从零开始计数。以此循 环下去。这种方法可以实现任意的偶数分频。-Dual frequency many times: even several times frequency should be more familiar with all the sub-fre
qiangdaqi1
- 这是一个数电的4选手抢答器的设计报告 内容详细具体 请查收-This one of the few -- six players Responder Design Report details specific Check-This is one of four players to answer in a few electrical device designed to report detailed and specific please check-This is one of the
alarm_judge
- 基于VHDL语言的闹钟音乐模块。改变状态机中的乐谱可以实现不同音乐-music unit based on VHDL. Changing rhymth in state machine in order to play different music.
bujindianji
- FPGA实现步进电机控制源代码。通过脉冲信号控制，产生一定频率脉冲的信号（脉冲频率用来控制速度），经过信号隔离放大（达到驱动电机的电压）来驱动控制步进电机-FPGA Implementation of stepper motor control source code. Controlled by the pulse signal, generating a frequency pulse signal (pulse frequency is used to control speed), vi
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
LCD_BY_CPLD
- LCD Interfacing Code using CPLD
SinglePhasePLL_v1.1
- 本代码是单相正弦电压锁相环程序，用于根据单相正弦电压生成其相位角度信息，包括：正交处理、坐标变换、PI运算、积分运算、取模运算等步骤。-This code is a single-phase sinusoidal voltages phase-locked loop program for generating the phase angle information based on single-phase sinusoidal voltage, comprising: an orthogon