资源列表
SPIADS7816
- SPI接口的ADS7816，其输出数据的格式是最高有效位(B11位)在前,当最低有效 位(B0位)输出后,若CS变为高电位,则一次转换结束,最高转换速度200kHz-。-This is the serial AD acquisition of reading and writing chip ADS7816 procedure for the Keil compilerthe output data format is the most significant bit (B11-bit) in
vhdl-44
- 4*4 vhdl语言键盘扫描程序 无去抖-4* 4 vhdl language keyboard scanner not to shake
a
- 利用430通过定时器输出不同频率的PWM波形用以驱动蜂鸣器发音-By using 430 timer PWM output waveforms of different frequencies to drive the buzzer sounds
pic16f54
- 通过控制scr来控制交流电的通断，实现智能开关-Through the control to control the SCR ac hige, intelligent switch
D-flip-flop
- Verilog的简单D触发器设计-Simple D flip-flop in Verilog design
demo110
- 状态机，检测状态110，小演示程序，可直接运行，verilog hdl-State machine, the detection state 110, a small demo program can be run directly, verilog hdl
SFIFO_8960
- 异步FIFO设计，简单适用，非常好用，节省资源。-Applicable asynchronous FIFO
ps_transfer
- verilog HDL语言编写的8位并串转换，使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ，can comprehense
VHDL_full_subtractor
- VHDL program_ A 4-bit subtractor by using 4 one-bit full-subtractor
frequency_cnt
- 频率计数器的设计，精确度不是很好，但是还是实现了功能。-failed to translate
mux
- 对20MHZ时钟进行分频。之后用分频后的频率作为时钟信号同步后级的模16计数器。4位计数器输出信号可以用来控制MUX进行数据通道的定时采集。-To 32 magnitude optional 20 MHZ clock frequency division.After using crossover frequency as the clock signal synchronization after level 16 counter modules.Four counter output sig
main3
- PIC18f26K22 main for Pulse width modulation(PWM).PIC18f26K22 main for Pulse width modulation(PWM).