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资源列表
shockware
- VHDL 波形防止抖动程序,学习试验材料-VHDL prevent jitter waveform procedures, the pilot study materials
config_ad6636
- 用Verilog正确配置ad6636，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad6636,, compiled in the ISE environment and realization of the right
fadder
- 利用两个半加器来组成的全加器，是简单的vhdl语言入门-The use of two and a half adder to form the full adder is a simple entry-vhdl language
ADC
- 灭火机器人头文件，功能程序和主程序部分 ADC.C,ADC.h,INTTASK.C,Public.h,RS232Comm.C-Fire-fighting robot header files, functions and the main part of the procedure ADC.C, ADC.h, INTTASK.C, Public.h, RS232Comm.C
ScanKey
- 在FPGA中用verilog编写的键盘扫描程序，返回时有中断-the program write by verilong which use to scan the switch and return inturrupt in fpga.
ad0809
- ADC0809 verilog-ADC0809 verilog...............................
ram_dp_sr_sw
- dual ram port in verilog
LED
- C5509上的键盘以及指示灯的驱动程序-DSP C5509 and the lights on the keyboard driver
digimotor
- DC Motor Control Program for AT89s52. in Keil C Uvision 3
zuoye
- 信号灯的简单控制程序，采用的是动态扫描方法！-Simple control program of the lights!
bayer_sensor_mod
- 基于verilog编写的 CMOS sensor 模型，可以输出bayer 数据，尺寸可调-Verilog prepared by the CMOS sensor model, you can output bayer data, size adjustable
Filter_Convolution_Example
- Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx