资源列表
SHUMAGUAN
- avr单片机 atmega16 数码管循环显示数字0到9-avr microcontroller atmega16 digital control loop display numbers 0 to 9
Rolling_Message_Modified
- PicBasic program for PIC16F876A for LCD display. Rolling message displaying for attractive look.
Freq_Divider
- frequency divider fpga get slow frequency
sn7448
- verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
fifo.v
- This the source code for FIFO -This is the source code for FIFO
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
install-vxworks62-xscale
- install txt for vxworks 6.2 intel-xscale license文件-install txt for vxworks 6.2 intel-xscale license
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
Decade-Counter
- decade counter with two input and count out outputs
sqrt
- 用verilog实现的开2次方，已经在modelism中经过验证，其时间周期不固定。-Implementation open square with verilog.
binbcd8
- Binary to BCD conversion in VHDL for implementation in FPGA
BCDto7Segment
- vhdl bcd to seven segment