资源列表
bi_bus
- 基于FPGA的双向端口的开发，该方法简单易懂，便于读者理解和应用-FPGA-based bi-directional port development, the method is simple and easy to understand, easy to readers to understand and apply
AGC
- 基于DSP的高质量AGC算法实现，本人原创-DSP-based AGC algorithm for high-quality, original I
serial2parallel256
- Complex Add in Vhdl with generic parameter
phaseconrol
- 将10Khz的输入信号经过分频得到两路互补的方波信号，方波信号的频率由分频计数初值决定。然后将分频后的方波进行移相，从而得到另外两路方波信号，移相的大小也由计数器的的初值决定。-After the 10Khz frequency input signals are two complementary square wave signals, square wave signal frequency by a frequency count of initial decision. And the
ADC_TCL5510-verilog
- verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz-verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz
FIBONACCI_SERIES
- fibonacci series in vhdl
WROM
- Twiddle factors in ROM
8jiance
- 使用verilog语言实现一个8选一的信号选择器-Use an 8 verilog language selected a signal selector
SPK
- 本程序基于51单片机C语言。利用蜂鸣器可实现效果： 影片里可以听到的定时弹快要爆炸时定时器发出的声音-The program is based on 51 single-chip C language. Effect can be achieved using a buzzer: Timer issued when the film can hear the sound of timed bomb about to explode
communication
- 此程序把接收的数据发送出去，波速率为2400。 测试此例子：打开串口调试软件，把波速率设置为2400， 向板发送一个字节数据，软件应能接收到同样的数据。-This program sends out the received data, velocity was 2400. Test this example: Open serial debugging software, the wave speed is set to 2400, Sends a byte of data t
clk-10divide
- 基于verilog编写的十分频时钟，简单易懂，欢迎大家下载和学习-Based on the frequency counter verilog prepared very easy to understand, are welcome to download and learn
01102
- 在最短时间内实现工作时间的安排，并使得收益最大化-In the shortest possible time work schedule and make maximize returns