资源列表
tut_signaltapII_verilogDE2
- Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in
signaltapII_verilogDE2
- This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implement
2410_iis
- s3c2410上移植ucos,并在ucos下实现iis音频功能-s3c2410 on transplantation OUT, OUT and under iis Audio function
digital-image-processing
- DSP5509 digital image processing程序代码-DSP5509 digital image processing code
lpc1700-LCD
- lpc1766驱动LCD例程，含汉字图形驱动。 开发板为LINPO-LPC1766,因为原板内容不全。-lpc1766-driven LCD routines, including Chinese characters graphics driver. Development board for the LINPO-LPC1766, because the original board incomplete content.
taxi
- 在Quatus下用VerilogHDL语言编写，实现出租车计价器功能
stm32f407-Key-and-LED
- stm32f407VET6 按键与LED例程，可以用按键控制LED与蜂鸣器。-stm32f407VET6 key and led example,key can control LED and buzzer.
GPIO
- STM32开发板的通用gpio例程，包括gpio配置，给io输出置1置0-STM32 development board GPIO routines, including GPIO configuration, to the IO output for 1 is 0
waterled
- LED3--LED10,由LED10开始循环亮，每1换个灯亮，按SW1就停止跳动，再按一下就继续再跳动-LED3- LED10, from the beginning of the loop LED10 bright lights for every one from another, according to SW1 to stop beating, and then click on the continue beating again
D_Clock
- 数字钟的主要功能有年月日时分秒的显示输出功能和对日期及时间进行设置的功能，还可以有整点报时等功能。设计数字钟的核心问题是时钟日期的自动转换功能。即自动识别不同月份的天数的控制。据此可以设计一个如图１所示结构的数字钟，该数字钟包括校时模块、时分秒计时模块、年月日模块、和输出选择模块。-digital clock is the main function Minutes date when the output function and the date and time set for the f
dianzheng
- 能在FPGA的板子上实现点阵的功能，利用QuartusII软件-Lattice function, use QuartusII software on the FPGA board
source_file
- FE42X单相防窃电电表DEMO(编译器 AQ430 AQ430 V2.0.6.5)-FE42X single-phase防窃电meter DEMO (compiler AQ430 AQ430 V2.0.6.5)