资源列表
ferescale-smart
- 全国大学生飞思卡尔杯智能车东北赛区进入全国赛程序-Freescale Cup National Smart Car University Students enter the national competition program in Northeast Division
AVR_USB1
- avr,单片机开发资料，usb1。1接口资料-avr, microcontroller development information, usb1. A data interface
VHDL
- VHDL培训教程，很好很强大！ VHDL培训教程，很好很强大！-vhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdlvhdl
PROFIBUS-DP
- PROFIBUS-DP现场总线智能节点的设计程序和源码电路图-Design of intelligent node based on PROFIBUS-DP
SKRETD(low_power)
- 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
730_basic_spi_module_v1.0.0.0
- This a program to perform Serial SPI communication using PIC micro controller-This is a program to perform Serial SPI communication using PIC micro controller
9111
- 凌华工控控制卡PCI-9111计数器采集卡使用例子，全功能-Industrial control card ADLINK PCI-9111 counter examples of the use of acquisition cards, full-featured
LM3Sxxx
- TI M3 Luminary LM3Sxxx原理图-TI M3 Luminary LM3Sxxx
digital-tube-dynamic-display
- STM8S105开发板 库函数 数码管动态显示-BoM entity electronic STM8S105 development board [library function] _ experiment 18_ digital tube dynamic display
9_TheBell
- FPGA，VHDL语言 蜂鸣器 响0.5S~~，时钟分频源程序，适用于所有FPGA芯片-FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE
- IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
mymidi
- 把PC键盘变成MIDi音符控制适配器电路单片机程序，midi协议，MIDI 文件格式结构等-use the PC keyboard into MIDi notes control adapter circuit SCM procedures, midi agreement MIDI file format structure