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  1. DAC

    0下载:
  2. TLV5630數位類比轉換器資料設定C源碼 -TLV5630 source digital to analog converter set
  3. 所属分类:ARM-PowerPC-ColdFire-MIPS

    • 发布日期:2015-06-26
    • 文件大小:121kb
    • 提供者:LIU ming
  1. dsPIC30F_AD

    0下载:
  2. dsPIC30F的AD轉換設定,讀取結果-dsPIC30F the AD converter to read the result set
  3. 所属分类:SCM

    • 发布日期:2017-04-16
    • 文件大小:21.69kb
    • 提供者:LIU ming
  1. hal_construction_in_UCOS_transplant

    0下载:
  2. USOS移植过程中hal的构建技术,中文pdf,USOS移植过程中hal的构建技术,中文pdf-USOS hal during the construction of portable technology, Chinese pdf, USOS hal during the construction of portable technology, Chinese pdf
  3. 所属分类:uCOS

    • 发布日期:2017-04-16
    • 文件大小:284.89kb
    • 提供者:张晓璐
  1. zigbe_application_notes

    0下载:
  2. Microchip Zigbee application notes: some important document to understand the microchip zigbee stack-Microchip Zigbee application notes: some important document to understand the microchip zigbee stack
  3. 所属分类:Embeded-SCM Develop

    • 发布日期:2017-05-19
    • 文件大小:4.89mb
    • 提供者:magma_25
  1. freeRTOS_V6.0.1

    0下载:
  2. freeRTOS_V6.0.1for the BHS-STM32 III Development Board
  3. 所属分类:ARM-PowerPC-ColdFire-MIPS

  1. CPLD_DEMO_OK

    0下载:
  2. 可以给VHDL初学者看的实例,全部经过验证-VHDL beginners can see examples of all the proven
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1.03mb
    • 提供者:王金凤
  1. PRIORITY_ENCODER

    0下载:
  2. A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:107.12kb
    • 提供者:swapnil
  1. BCD_COUNTER

    0下载:
  2. Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:60.67kb
    • 提供者:swapnil
  1. xiyiji

    0下载:
  2. 这是用单片机实现一个全自动洗衣机程序,利用软件仿真实现!-This is a fully automatic washing machine with MCU program, the use of software simulation to achieve!
  3. 所属分类:SCM

    • 发布日期:2017-04-06
    • 文件大小:83.83kb
    • 提供者:1212
  1. parity_generator

    0下载:
  2. parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd num
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:20.44kb
    • 提供者:swapnil
  1. randon_numder_generator

    0下载:
  2. random number generator it generate random number continousely on clk pulse
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-23
    • 文件大小:2.54kb
    • 提供者:swapnil
  1. comparator

    0下载:
  2. comparator it comparea two input and give its output
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:1.15kb
    • 提供者:swapnil
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