资源列表
dig_pll
- 一个简易的数字锁相环，可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock
Chapter_4-4_Compile_and_Program_uCos2
- FriendlyARM English User Manual Chapter 4.4 Compile and Program uCos2
test
- uC/OS-II example. There is a three basic task-programming application which uses uC/OS-II. Educational purpose only.
u-boot-090801
- U-Boot源码, 开发板常用的BOOT，能兼容大部分小机。-U-Boot source code, development board commonly used BOOT, compatible with the majority of small aircraft.
DS1302
- 12864+DS1302时钟+18B20温度计-12864+ DS1302 thermometer clock+18 B20
AD
- ad 转换资料，内有AD574，AD0809，C语言程序-ad
chuzucheVHDL
- 用VHDL写的出租车计价程序，拥有详细的说明-Taximeter written with VHDL program, has a detailed descr iption of
freescale
- 飞思卡尔智能车的舵机测试程序 用飞思卡尔官方提供的工具下载到S12单片机-Freescale' s Smart car steering test procedure using the tools provided by Freescale' s official download S12 MCU
C
- 一本讲嵌入式c/c++的精华。学嵌入式的朋友可以下来看看。-A talk Embedded c/c++ is all about.
manch
- 该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design
minigui
- helloword for no_name-helloword
sumador
- sumer vhdl code for FPGA of Xilinx