资源列表
FSA506
- FSA506 display controller
FPGA
- 里面有用NIOS2与SOPC的做的一个串口程序，还有详细文档步骤，对于学习SOPC者有很大帮助-Inside useful NIOS2 to do with the SOPC a serial program, as well as detailed documentation steps, for the study were of great help to SOPC
qtmcom_loop_onetoone
- 可实现两个串口互相通讯，界面友好，在Qt4环境下可直接运行。-realized between two serial communications, user-friendly, in Qt4 environment can be directly run
SPI5045
- 单片机和5045通信，是SPI通信，程序在硬件上实现了。-5045 microcontroller and communications, is the SPI communication, the program implemented in hardware.
qt_read_ini
- 用Qt4编写的显示界面，并且实现对ini文件的读写操作-Written using Qt4 ，and realize the ini file to read and write operations
finallab
- introduction to veri well and behaviural modeling code for 4 to 1 mux
stepper
- 51单片机控制5804驱动芯片驱动步进电机，速度值通过spi接口（软实现）通讯存储在外部eeprom上，断电不丢失。-51 SCM control 5804 driver chip to drive a stepper motor, the speed value is through the spi interface (soft implementation) communication is stored in the external eeprom, the power is not l
FINALAB
- it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
encoder_binary
- 一个简单的FPGA实现的编码器，但程序中有详细的说明，并附有测试凳，可以以此为基础设计更复杂的编码器-FPGA realization of a simple encoder, but the procedure described in detail, together with a test bench, you can as a basis for designing more complex encoder
8BITCONDITIONALSUMADDER
- it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell
FIFO
- 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
FIR_lowpass
- 在FPGA上实现一个FIR滤波器，适当修改滤波器参数，就可以运用于自己的工程中-In the FPGA to achieve a FIR filter, appropriate changes to filter parameters, you can apply your own project