资源列表
uboot_tiny4412-20130729
- exynos 4412 u-boot Development Kit, Samsung source plant to provide, FriedlyARM transplant
Zigbee_P2P_2012.11.23
- CC2530芯片，点对点无线数据互传范例-CC2530 chip, point to point wireless communication paradigm
4463-51demo
- SI4463无线收发DEMO，基于51单片机，具有很好的学习价值，并且最新的SI4463芯片功能与距离远强于SI4432-SI4463 wireless transceiver DEMO, based on 51 single chip, and has good value of learning, and the SI4463 chip function and distance of the latest far stronger than SI4432
arduino-motor-control
- 通过下位机（arduino）控制步进电机并实时测量相关数据，通过USB 上传到上位机（PC），可以实时保存数据。-By lower machine (arduino) stepper motor control and real-time measurement data, upload to PC via USB (PC), you can save the data in real time.
Count-clock-synthesis-experiments
- 练习综合设计能力，设计一个含时/分/秒的时钟，并且可以设置、清除、 12/24 小时工作模式切换。-Exercise comprehensive design capabilities, including the design of a time/minutes/seconds of the clock, and you can set, clear, 12/24 hour work mode.
dianzhen_time
- 32*64点阵模块时钟，变换字体，可以显示农历!-32* 64 dot matrix module clock, change the font, you can display the Lunar!
wigen_decode
- 韦根解码程序及电路，51单片机，可以传输卡号-Wiegand decoding procedures and circuit
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计，了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
Four-quiz-Responder
- 运用VHDL语言实现四路智力竞赛抢答器。抢答器的主要功能模块是是：1、对第一抢答信号的鉴别和锁存功能；2、计分功能。3、数码显示 ；4、答题限时功能。在本设计主要讲述抢答、计分和警告的功能。-Using VHDL language quiz four Responder.Responder main function modules are: 1, for the first answer to identify and latch signal 2, scoring functio
exp5
- 用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full a
RS485
- 这是基于飞思卡尔十六位单片机的RS485通信的例程-freescale RS485 routine
PLL
- 这是基于飞思卡尔十六位单片机的锁相环程序-freescale PLL routine