资源列表
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
PCI_arbi
- PCI总线仲裁参考设计Verilog代码。最大支持6个master的仲裁。-PCI bus arbitration reference design Verilog code. Maximum six master arbitration.
interrupt
- 这是自己写的一个中断函数，用studio写的-This is written an interrupt function, with the studio to write
Altera-FPGA_CPLD-design
- 《Altera FPGA-CPLD设计》一书的实例源代码。非常适合FPGA初学者。-" Altera FPGA-CPLD design" book source code examples. Very suitable for FPGA beginners.
Timer
- LCD12864驱动程序，里面有一个时钟程序。-LCD12864 driver, there is a clock program.
FPGA-design-and-development-examples
- < FPGA数字电子系统设计与开发实例导航>>的实例代码，包含I2C，URAT，USB，CAN等等。-< <FPGA数字电子系统设计与开发实例导航> > Example code, including I2C, URAT, USB, CAN, and so on.
Cbuitidig
- 可以实现设置字体颜色标题等文件属性及和打印机连接打印文件-You can set the font color title the file attributes and print the file and printer connections
SHT11
- SHT11很难得的中文资料，附带80C51事例程序-SHT11 difficult to get the Chinese data, incidental 80C51 examples
Bulkloop1
- CY7C68013固件，从FIFO模式，CPU不参与数据传输，使用EP2 和EP6端点，同步模式，批量传输模式-CY7C68013 firmware from the FIFO mode, the CPU does not participate in data transmission, using EP2 and EP6 endpoint, synchronous mode and bulk transfer mode
ran_num_generator.tar
- vhdl random numbergenerater
6bitLEDdisplay
- 6位LED数码管显示的C语言程序。附有源代码和说明文档。-6 LED digital tube display C language program. With source code and documentation.
karman_text
- 最简单的方法实现卡尔曼滤波，本程序可实现站立。-The easiest way to achieve the Kalman filter, the program can achieve standing.