资源列表
ARM.cortex-M3.SSI.SysTick.SysCtl
- ARM cortex-M3系列处理器的代码，包括同步串行接口SSI、系统节拍定时SysTick、系统控制SysCtl。（IAR环境工程）-ARM cortex-M3 family of processors code, including synchronous serial interface SSI, the system beat timing SysTick, system control SysCtl. (IAR Environmental Engineering)
ARM.cortex-M3.Interrupt.QEI.hw_types
- ARM cortex-M3系列处理器的代码，包括正交编码器接口QEI、中断控制Interrupt、硬件类型定义hw_types。（IAR环境工程）-ARM cortex-M3 family of processors code, including quadrature encoder interface, QEI, interrupt control Interrupt, the hardware type definition hw_types. (IAR Environmental Eng
ARM.cortex-M3.experiment.code.1
- ARM Cortex-M3 系列处理器 的实验代码，内容很全，涉及片内和外围所有部件编程。（Keil环境）-ARM Cortex-M3 family of processors experimental code, content is very wide, involving all the components and peripherals on-chip programming. (Keil environment)
ARM.cortex-M3.experiment.code.3
- ARM Cortex-M3 系列处理器 的实验代码，内容很全，涉及片内和外围所有部件编程。（Keil环境） -ARM Cortex-M3 family of processors experimental code, content is very wide, involving all the components and peripherals on-chip programming. (Keil environment)
ARM.cortex-M3.experiment.code.4
- ARM Cortex-M3 系列处理器 的实验代码，内容很全，涉及片内和外围所有部件编程。（Keil环境） -ARM Cortex-M3 family of processors experimental code, content is very wide, involving all the components and peripherals on-chip programming. (Keil environment)
CD-PPARM-USB-BASE-2_21_0
- OS IAR PowerPac™ USB for ARM v2.21-OS IAR PowerPac™ USB for ARM v2.21
pparm_usb-v2_21_keygen
- Keygen for IAR PowerPac(TM) USB for ARM Base edition v2.21
pparm_tcpip_v2_21_keygen
- Keygen for IAR PowerPac(TM) TCP/IP for ARM Base edition v2.21
LPC21xx
- LPC21xx系列处理器，通用寄存器列表，这是我培训过程中导师总结的。-LPC21xx series of processors, general-purpose registers list, this is my summary of the training course instructor.
PWM
- ＡＲＭ２３ｘｘ芯片的ＰＷＭ程序，包括工程-ARM23xx chip PWM process
armppthtml
- 初学者 仔细看看 很有帮助 还可以再网上下点课件 对照看 效果也不错-Beginners can also be helpful to take a closer look online to see the next point of the control effect is good courseware
mips-iv
- MIPS 指令集，比see mips 更适合用作手册使用-This appendix describes the instruction set architecture (ISA) for the central processing unit (CPU) in the MIPS IV architecture. The CPU architecture defines the non-privileged instructions that execute in user mode.