资源列表
Wireless_Communication_FPGA_Design
- 通信经典书籍《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，学通信的人有福了-Wireless_Communication_FPGA_Design
FpgaDesignOfWirelessCommunicationsCodeExamples
- 无线通信fpga设计代码实例，包括MATLAB和Verilog HDL 语言实例，供大家学习和研究-Fpga design of wireless communications, code examples, including examples of MATLAB and Verilog HDL language, for them to learn and study
PWM_VerilogHDL
- altera公司网站上的详细的PWM设计的Verilog hdl源程序，大多数都采用这个-altera company' s Web site the detailed design of the PWM source Verilog hdl, most have adopted this
modelsim
- modelsim详细使用说明，介绍详细。适合仿真测试初学者使用。-modelsim detailed instructions for use, introduced in detail. Simulation tests for beginners to use.
PCI_VHDL
- vhdl实现pci，找了很久才下到。应该比较适合设计-vhdl implementation pci, looking for a long time before the next to. Should be more suitable for design
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO
FRE
- 用1602显示的等精度频率计，有多种功能的；可能测试占空比和周期的-vhdl
reedsolomon
- reed solomon encoder synthesis and simulation is done using verilog and working fine
ddsm
- 用vhdl实现dds功能的程序试一试看看是不适合你！-Dds feature using vhdl program to try to achieve a look is not for you!
uart
- uart-universal aynchronious reciever and transmitter used to connect the pc and fpga to pass the data
Verilog
- altera公司推荐的verilog代码风格教程-altera recommended verilog code style tutorial
f_adder_4bit
- 四位二进制全加器，用原理图输入的形式实现，在Quartus II 5.1下编译通过。-4 binary full adder, with schematic input in the form of implementation, compiled in the Quartus II 5.1 adoption.