资源列表
UART
- 包含一个在QUARYUS环境下运行的UART的工程，实际在EP2C20Q240上调试成功的通用串口VHDL程序-The QUARYUS environment contains a UART to run the project, the actual success of the EP2C20Q240 Universal Serial debugging VHDL programs
DATA_get
- 基于Fpga的高速数据采集系统设计，可以利用这个系统高速采集数据。-Fpga-based high-speed data acquisition system design, can be used by high-speed data acquisition.
FPGA_VHDL_sinusoidal_function
- 该文件包含基于VHDL的正弦信号发生器的设计源码-This file contains the VHDL-based design of sinusoidal signal generator source code
dff
- 关于DFF的FPGA实现，有VHDL源码-On the DFF of the FPGA implementation, there are VHDL source code
UARTReceiver
- serial communication using uart FPGA-based embedded system
Freq_Divider
- frequency divider fpga get slow frequency
DE2_PWM
- RC servo controller system using DE2
asymmetric_fifo
- 高速同步非对称FIFO,verilog 代码，很有价值的参考设计。-Asymmetric high-speed synchronous FIFO, verilog code, and very valuable reference design.
statemachinecontroller
- it is a vhdl code for a state machine controller
150M
- quartus_nios 综合开发平台，可以多中断，重要的是它的cpu可以工作在150M，总线工作在100M×32bit；-quartus_nios comprehensive development platform that can interrupt more important is that it' s cpu can operate at 150M, bus work in 100M × 32bit
0_F
- 译码（把二进制转化成十进制，七段码）vhdl语言，适用于初学者-yima
hexc_display
- 数码管显示的VHDL程序，自己做实验调出来的-LED display of the VHDL program, tune out their own experiments