资源列表
vhdl-xiyiji
- 基于quartus2的vhdl状态机——洗衣机编程应用，采用EDA自顶向下的设计方法。-The vhdl state machine based quartus2- washing machine programming applications, the EDA top-down design approach.
mult16s
- 16位乘法器，VHDL语言编写的，供大学交流学习-16-bit multiplier
Traffic_Light_Final
- Traffic light written with Verilog-written with Verilog
Single_pwm
- 这是一个生成pwm波的程序，使用按键改变占空比的大小，通过增加按键的消抖程序能够精确控制占空比的变化。(This is a program to generate pwm wave, use the button to change the size of the duty cycle, by increasing the key of the shaking program can accurately control the duty cycle changes.)
exp2prj1
- 基于FPGA的DDS，编写语言为verilogHDL，编辑环境为quartusII 9.0，dds频率可程控调节-a Direct Digital Synthesis based on FPGA
CIS_drive
- 一个接触式图像传感器的驱动，Verilog语言，内含规格书-A contact image sensor driver, Verilog language, containing specifications
FIR_Final
- Finite impulse responce filter
step
- 步进电机细分驱动系统可以实现使用或不使用细分，电机正反转控制-Subdivision stepper motor drive system can be achieved with or without breakdown, motor reversing control
16bitalu
- 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
SDRAM
- 基于SDRAM的存储器接口设计，采用verilog编写-SDRAM memory interface design based on
EXP4
- FPGA系统设计，通过他可以让初学者更快的入门，对嵌入式开发有更深的认识。-FPGA system design, beginners of practice good tools
uart
- 串口的实现代码，用verilog编写的，并附有仿真文件。-Serial implementation code written using verilog, together with simulation files.