资源列表
lab
- VHDL Lab manual useful for experiment purpose
dds
- 反映测试，测试反应的时间，达到在滚定时间按下会显示你花费时间。-Reflect the test, test the reaction time to achieve the given time in the roll press will show you spend time.
clock_lcd1602
- 在DE2-70上可同时实现数码管和LCD1602上动态显示电子表的数字。-In DE2-70 can be at the same time in the digital tube and LCD1602 dynamic display of the electronic watch value.
alteraipcore
- Altera公司的15个ip核的源代码，找了很久才找到的一些常用ip core-Altera 15 nuclear source ip
modelsim-for-verilog
- verilog或VHDL编辑仿真软件的使用方法，个人用过觉得很不错，所以在此推荐给大家-editing verilog or VHDL simulation software to use, personally feel very good used, so this recommendation to you
DA5
- SPARTAN SAN STARTER KIT 上的DA控制器的驱动程序。该DA为LTC2624，SPI接口。已用正弦波数据测试过了，请放心下载。-SPARTAN SAN STARTER KIT of DA controller driver. The DA for LTC2624, SPI interface. With sine wave data has been tested, please feel free to download.
reaction-timer
- reaction timer by verilog
3-8译码器
- vhdl的3-8译码器-instantiate the 3-8 decoder
59-50-(2)
- 本人的课设电子时钟VHDL 50秒开始嘀嘀嘀 报警。包含总文件-My lesson an electronic clock tick VHDL 50 seconds to start beeping alarm. Include the total file
lcd_test
- Xilinx Spartan-3E实验板上基于verilog控制lcd屏幕A到Z反复轮转显示。-Xilinx Spartan-3E verilog based test control board lcd screen A to Z repeated rotary display.
VGAinterfacedesigexamplesandtestprocedures
- VGA接口设计实例及测试程序 实验通过-VGA interface design examples and test procedures
32Kfft
- 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later