资源列表
PROJECT
- 这是LVDS的测试源文件，经运行后正确。-this is a lvds Programme.
VHDLfenpin
- VHDL进行分频的完备资料,包含偶数、奇数、小数、分数-VHDL for the completeness of the information divide, including even and odd numbers, decimals, fraction
Quartus_Common_Error_And_Warning_Analyze
- Quatus常见错误汇总与分析 该文章来源 :一是来自网上几处出处的汇总 二是来自作者本人应用过程中遇到的问题。 可以帮助大家解决烦人的quartus警告和error 仅供参考 -Summary and analysis of common mistakes Quatus the article Source: First, a summary of provenance from the Internet a few second is from the author
DivideByNCounter
- This folder contains the DividebyNCounter using verilog HDL -This folder contains the DividebyNCounter using verilog HDL
QuartusII_Warning_analyse
- quartus2警告信息解决办法补充说明。 -quartus2 warning message solution supplement. quartus2 warning message solution supplement.
16bit_pipeline
- 16 bit pipeline design by vhdl.
as2
- 这是关于Vhdl编程语言的基础。讲述了硬件 描述语言及其编程特点-This is about Vhdl programming language foundation. Described the characteristics of the hardware descr iption language and its programming
Luces_Secuenciales
- SEQUENTIAL LIGHTS WITH STROBER EFFECT IN VHDL FOR FPGA
FILTRO_DIGITAL_EN_VHDL
- DIGITAL FILTER IN VHDL FOR XILINX FPGA SPARTAN 3
FINAL
- MESSENGER BETWEEN 2 FPGA WITH PS2 KEYBOARD CONTROLLER AND VGA CONTROLLER USING SERIAL TRANSMISION
countall
- 时钟总片,有年月日分钟秒钟，秒表，三个闹钟，调时。总共需要三个控制键-clack system
VHDL_100example
- vhdl编程100例，初学者可以参考下，希望对大家有帮助-vhdl programming 100 cases, beginners can refer to, hopefully help to everyone