资源列表
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
examples
- Verilog源程序130例，对初入门者非常有用。-Verilog source code 130 cases, were very useful for beginner.
movedata
- 按照一定格式把一段数据放在内存上，然后输出在屏幕上-my asm
controller
- PI controller and its source code
updown_6
- 这是一个使用VHDL语言编写的六进制计数器，具有自动控制加计数或减计数的功能。-This is a VHDL language using the six binary counter, with automatic control plus or minus count count function.
counter_12
- 使用VHDL语言编写的十二进制计数器，有异步清零、同步置数的功能、-Using the VHDL language of the 10 binary counter, there are asynchronous clears, synchronous set the number of functions,
calc_v2_s3eboard
- Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
keyboard
- verilog实现键盘驱动功能，具备基本字母按键输入，大小写转换功能，通过串口与主机实现交互-verilog to achieve keyboard-driven features, basic letter keys input, case conversion functions, interact with the host computer through the serial port
shudian
- 数字钟相关程序，能实现时间的自动跳动，还能改动时间，整点报时-Digital clock-related procedures, to achieve the automatic beating of time, but also changes in time, the whole point timekeeping
CPU16
- 自己用VHDL写的16位的CPU，在学校的课程上通过了测试。-Own use VHDL to write a 16-bit CPU, in school curriculum passed the test.
DM642_network_video_source
- DM642_network_video_source 我们研究所里用的程序，很通用的-DM642_network_video_source our graduate program to use, it is common
IIR
- 实验说明： 本次实验实现一个IIR滤波器，并在ISE里面仿真。 project目录里面是工程-Experiment descr iption: this experiment to achieve an IIR filter, and the ISE inside the simulation. \ rtl directory which is the source file \ project directory which is the project