资源列表
dual_RAM
- vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
8psk
- 利用DDS原理设计8psk的原代码，已通过调试-8psk principle design using DDS source code, which has passed the commissioning
Pk-1k30DEMO
- 几个关于VHDL的几个经典的例子，对于学习VHDL语言和FPGA设计有很大的帮助-Few questions about a few classic examples of VHDL for the VHDL language and FPGA design study of great help
cunchushiboqi
- 用vhdl编写数字存储示波器，通过调试，仿真环境是maxplus-Vhdl digital storage oscilloscope with the preparation, through debugging, simulation environment is maxplusII
A8255V4
- A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.
nios-Function
- nios2的函数手册， nios2的函数手册-nios2 function manual, nios2 function manual, nios2 function manual
nios-components
- nios2的5个列子， nios2的5个列子-nios2 of 5 Liezi, nios2 of 5 Liezi, nios2 of 5 Liezi
cycloneiii
- cycloneiii引脚分配图 excel版本-cycloneiii pin assignment plan excel version of the
VHDLFPGA
- 可编程逻辑器件教程，WORD版本，夏路易编-Programmable logic device tutorials, WORD version, Xia Luyi compiled
VGA_v
- 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input
I2C
- 使用VHDL写的标准 IIC代码 标准的接口文件，具有三态功能-The use of a standard IIC write VHDL code for a standard interface file, with tri-state function
pudn
- VHDL写的SDRAM的精简控制器。包含SDRAM接口控制器，和数据读写控制。含有实际抓取的signatap波形。为初学SDRAM者的，最好参考。-A SDRAM controller written in VHDL.Including SDRAM interface controller, read and write control. It is the best reference for SDRAM learners .