资源列表
clock
- 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
clock
- verilog hdl代码 实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
xilinxfpga
- Xilinx FPGA VerilogHDL 典型入门实例-Xilinx FPGA VerilogHDL
deinterleave
- CDMA.1X中，解交织的FPGA实现，程序基于VHDL编写，在XILINX开发板实现。-CDMA.1X, the solution of interwoven FPGA implementation, the program prepared based on VHDL, in the XILINX development board to achieve.
timer_set
- 这个是我自己编写的verilog代码，实现的功能是，在数码管上显示时间，按一个键，显示日期，长按一个键，显示秒表。。。时间日期可调-This is my own code written in verilog to realize the function of the digital tube display time, press a button, display the date, long press of a button, display Stopwatch. . . Time a
PS2-VGA
- VHDL- introduce keywords from keyboard and displaying on a VGA display
VHDL_code_forth-CPU
- this is amazing code for a forth processor-this is amazing code for a forth processor
program_with_all_details
- simple 8085 progam with all explainations
finBlockDiagram
- this a functional blosk diagram for a digital signal processor-this is a functional blosk diagram for a digital signal processor
Signal-Processing-Using-Digital_Technology
- Signal Processing Using Digital Technology FOR HARDWARE DESIGN
dlx
- 一个简单的流水线cpu程序，具有加减乘除，移位等功能。-a simple stream