资源列表
dzqfinal
- 基于vhdl的电子琴源程序， 基于vhdl的电子琴源程序。-Vhdl source code based on the organ, the organ-based vhdl source code, based on vhdl source of the organ.
attachments_2010_01_29
- dct and idct vhdl code
viterbi
- verilog code for viterbi encoder and decoder
Design_of-8_Bit_Microcontroller
- vhdl code and tutorial for 8 bit microcontroler
ic_design_flow_vhdl
- vhdl code and icdesign flow for mentor graphics ic design tools
E1Tsi_TB
- TSI testbench for E1
FreqSynth
- Frequency synth example with primitives. Very simple.
AciAudioClks_TB
- Audio Codecs Clks synth for tlv
baudTest_TB
- baud testbenchfor sync and assync serial communication
E1SyncPkg
- The package constructor for E1sync example.
lcd
- FPGA控制lcd1602(verilog)-FPGA control lcd1602 (verilog)
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display