资源列表
jkmk
- 用EDA编的程序 是关于电子钟的很有参考价值-The program is compiled with the EDA on the electronic clock of great reference value to
ASK0908272
- 自己写的二进制频移监控程序，包含testbench,供大家参考-this is the AsK programme,including testbench
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
twodct
- 两种快速DCT算法的矩阵分解与分析。两种dct的对比。
ALU8
- ALU8 is the block in Verilog Digital System Design
Steppermotor
- 步进电机定位控制系统的VHDL描述与仿真，源文件附有注释-Stepper motor positioning control system, VHDL descr iption and simulation, source files annotated
Digitalfrequency
- 数字频率计VHDL程序与仿真,附有仿真截图和源程序注释-Digital frequency meter VHDL procedures and simulation, with simulation screenshots and source code comments
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
bin_copy
- FPGA驱动12864汉字显示源代码，12864是16个引脚的带字库的液晶显示模块-12864 Chinese character display FPGA-driven source code, 12864 is a 16-pin LCD display module with a font
v74160
- This file is the implementation of 74160 in VHDL codes and can be synthesized.
YYPP
- 计算机组织与系统结构实验 用一个74182芯片和四个74181芯片构成一个4位逻辑算数运算器，实现平台为Cyclone II EP2C35F672C6-Computer Organization and Architecture Designing for Performance Experiment