资源列表
dds_final
- 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjusta
OCIDEC_Drivers
- OCIDEC ATA driver source code
VHDL
- VHDL 语言要素，可以帮助初学者，加深理解-VHDL
f_h_v
- this file describe how to recupere the signals from a video signal when it out from an ADV7180 chip.
ADV7180.vhd
- this files describe how to configure an ADV7180
ADV7180
- this files describe how to configure an ADV7180a
422
- files describe how to configure ADV7180- files describe how to configure ADV7180
CONFIG_REG
- this files describe how to configure an ADV7180this files describe how to configure an ADV7180
Altera_Quartus_6.0_crack
- fonctional crack of VHDL describer Quartus 6.0
vhdl
- ldpc编码的vhdl的实现，一种802.13的方式-ldpc coding vhdl implementation, a 802.13 a way
DE2_LED_ON
- 一个简单的led闪烁程序，检测DE2学习板的led灯，用verilog语言编写-A simple blinking led program to petect learning DE2 board led lights, with the verilog language
FLASH_SDRAM
- 利用QUARTUS II的SOPC设计的Nios II系统，检测Flash模块和SDRAM模块是否可用。对于设计之前的模块检测有一定参考价值。-Use of QUARTUS II of the Nios II system, SOPC designs, testing Flash module and SDRAM module is available. Prior to testing for the design of the modules have a certain reference