资源列表
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
counters
- 用VHDL编写的最大值为255的计数器，供初学者参考-A 255 counter of VHDL，for Beginners Reference
conditioner
- VHDL设计的空调系统有限状态自动机，带有VHDL测试平台代码-VHDL design of air-conditioning systems finite state automata with VHDL testbench code
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
idt723641
- VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use
PID-controller
- 用VHDL设计的PID控制器，带有VHDL测试平台代码-PID controller designed with VHDL,with VHDL testbench code.
divider
- 用VHDL编写的多次分频器，带有VHDL测试平台代码-Multiple frequency divider with VHDL testbench code
MCU_to_FPGA
- FPGA与单片机通信的代码，采用VHDL编写，已验证过-FPGA and MCU communication code, the preparation of VHDL has been verified
lcd_12864
- lcd12864带中文字库的显示程序，采用状态机的方式实现，已验证过的-lcd12864 with the Chinese character display program, using the state machine ways, has been verified
CodedLOCK
- 基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释-FPGA-based design and implementation of electronic locks, language is VHDL language, annotated