资源列表
CPLDpro
- 模拟量输入卡CPLD程序，包括比较器，计数器等。-Analog Input Card CPLD procedures, including comparators, counters and so on.
巴克码VHDL
- 非常详尽的VHDL语言编写的巴克码发生器，已在QuartusII上运行，检查无误
FPGA
- fpga实现图像的变换，图像旋转放大-fpga implementation image transform, image rotation and magnification
CPLD-FPGA
- CPLD FPGA嵌入式应用开发技术白金手册配套源码-CPLD FPGA embedded application development technology platinum manual matching the source code
keyqudou
- fpga verilog hdl 设计键盘去抖动程序，设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
mux4booth
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ，quartusii 9.0 ，2booth 4bit
top_module
- fpga 使用verilog hdl 语言，quartusii 9.0编程环境，设计的4个led灯分别实现不同功能，然后由一个顶层文件调用，完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called,
WASHING-MACHINE-2012Verilog
- Verilog语言编写的自动洗衣机控制程序，数字系统课程设计-Verilog language automatic washing machine control program, digital systems curriculum design
FIFO
- Simulation and Synthesis Techniques for Asynchronous FIFO Design
ADC
- CPLD ADC采集控制源码CPLD ADC采集控制源码-CPLD ADC
CummingsSNUG2002SJ_FIFO2
- Simulation and Synthesis Techniques for Asynchronous FIFO Design2
manchester
- manchester ABOUT CPLD 应用数字通信应用端口-manchester ABOUT CPLD