资源列表
08-Multiplexers
- vhdl code for adder for quartus
clk_divider
- Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
E8051_256
- This contains the main-level VHDL files required for an example complete, ready-to-use, FPGA/ASIC 8051 microcontroller. The corresponding main schematic can be found in the Schematics folder, and a technical descr iption of the e8051 core inter
ds18b20_verilog
- 用verilog语言编写，实现DS18B20测量温度的程序，包括整个工程文件。-Using verilog language, achieve DS18B20 temperature measurement procedures, and including the project file.
jiafaqi
- 用Veriloge编的四位二进制加法器。用一个显示屏进行显示。-Veriloge series with four binary adder. With a display to display.
DE2_CCD
- FPGA 上实现VGA控制器 开发平台为altera官方开发板de2 -DE2 FPGA VGA LCD
communicationFPGADesign
- 包含matlab和Verilog两中代码：主要功能是关于无线通信的-contain：matlab and Verilog codes about communication
viterbi
- 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
hdlsrc_new
- CIC滤波器实现，级联FIR，节省资源-CIC filter
VGA_test
- 基于FPGA设计的一段测试VGA接口的VHDL小程序\功能为在显示器上间隔显示横条、竖条以及棋盘格等彩条信号，希望对初学FPGA驱动VGA接口的电子爱好者有用-FPGA-based design of a VGA interface VHDL test applet \ functions for the intervals shown in the display bar, vertical bars and checkerboard patterns and other signals of
Soda_Machine
- drink machine finite state machine
fifo.v
- This the source code for FIFO -This is the source code for FIFO