资源列表
clock_divider
- clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
SEG7_Timer
- 七段数码管时钟显示的verilog程序，开发环境quartusII7.0-Seven-segment digital tube display clock verilog program development environment quartusII7.0
clock
- 可调式时钟，可对时钟每位进行加减，被调整位闪烁显示-Adjustable clock, each clock can add or subtract, to be adjust-bit flash display
PWM_LED
- 利用PWM控制LED亮灭的verilog程序，开发环境quartusII7.0-Using PWM control of LED light off a verilog program development environment quartusII7.0
xapp202
- 在ATM应用中实现内容寻址寄存器（CAM）-In the ATM application to achieve content addressable register (CAM)
dds
- 高精度高速正弦波生成，正弦波相位和正弦波频率可调。-make sin
RGB_TO_YUV
- converter rgb to yuv
Codeur_SP
- quadrature encoder state machine
DC_Removal
- DC removal vhdl code
derotator
- derotator for qam with sin and cos lut
Xilinx090214
- 该文档中含有Xilinx 实验板入门程序15个，程序经典简洁，-The document contains a Xilinx development board entry process 15, the program classic simplicity,
B1
- Begining code for manhester decoder