资源列表
dianlucheshi
- 100列VHDL的开发实例，用于FPGA的初学者-100 examples of VHDL development, for beginners
finished369phase1
- phase 1 of mips computer architecture
vhdl_source
- 函数发生器VHDL语言实现递增，递减锯齿波，方波，正弦波，阶梯波的实现-VHDL， function ,delta, sin, ladder ,isaw dsaw
vhdlExamples
- VHDL 设计模块 例程 若干个 -several examples of VHDL design~~~~~~~~~~~
fpga
- 基于EasyFPGA030的模拟开小车的设计和模拟乒乓比赛设计。-To open car simulation based on EasyFPGA030 design and simulation table tennis game design.
fpga1
- 基于EasyFPGA030的直流电机控制电路设计和四位数字密码锁。-DC Motor Control Based on EasyFPGA030 circuit design and four-digit combination lock.
fpga2
- 基于EasyFPGA030的波形发生器设计和串口接收显示设计。-The waveform generator based on EasyFPGA030 serial receiver design and display design.
ActelFPGA_PCI
- 本文档介绍通过 Actel Flash 的FPGA 来实现PCI 的桥接芯片的功能。-This document describes the FPGA by Actel Flash to achieve PCI bridge chips.
ADC_TLC549
- TLC549的VHDL驱动源码 已测试通过的TLC549的驱动源码 有转换使能和转换完毕标志-TLC549 the VHDL source code has been test driving the driving source through the TLC549 has converted to energy and the conversion complete flag
clkdiv
- 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
smart
- 周立功的SmartEDA中的串口源码，照着书本敲入电脑的-ZLG' s SmartEDA the serial source code, according typing computer books
FIFO
- 速度高达130MHz 可实现高速数据采集 程序源码为Verilog-Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog