资源列表
project4
- 设计一个14阶FIR滤波器，已给出滤波器系数以及验证程序-A 14-stage FIR filter design, has given the filter coefficients and the validation process
ADController
- For Analog Device 7808/18/28 SPI Controller
MACHINE
- vhdl 实现的洗衣机管理系统 仿真通过的 -vhdl simulation to achieve the washing machine management system adopted
icnado_newgood_pinlvji
- 使用ISE编译的频率计，可测最低频率范围1hz，最高根据系统时钟决定-ISE compiled using the frequency meter, the lowest measurable frequency range 1hz, the highest decision according to the system clock
LCD_PS2
- DE2的鼠标IP核的完整套件。使用altera_up_avalon_ps2。有lcd-Mouse IP core DE2 complete package. Use altera_up_avalon_ps2. There lcd
qingdaqi
- 实现8路选手抢答，抢答时间调整，回答时间调整，回答倒计时显示灯-Achieve 8 players Responder, answer in time to adjust, time to adjust to answer, the answer countdown indicator
jiaotongdeng
- 实现十字路口的交通灯控制，分主干道和次干道显示。-traffic lighter，display
keyboard
- 用VHDL语言实现4*4键盘的识别，扫描键盘，译码并点亮开发板上相应led-4*4keyboard，VHDL
VerilogQuickRef
- Verilog Quick Reference
verilog-digitaldesign
- Verilog digital design
jishufenpingqi
- 记数分频器 记数分频器 记数分频器-记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器记数分频器
pwm
- 用VHDL语言 描述 生成pwm的 IP核-Pwm using VHDL language to describe the generation of IP core