资源列表
MP3-design-using-verilog
- 基于Xilinx XUPV2P平台(FPGA开发板)的MP3播放器设计-MP3 player design based on the the Xilinx XUPV2P platform (FPGA development board)
DDS-design-based-on-verilog
- 用verilog语言设计DDS数字频率合成器-DDS design based on verilog
Fast-adder-design-using-verilog
- 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
typing
- 以通过单片机按键弹奏乐曲单片机采用打字, 喜欢VHDL的朋友可以下了看下-51 single-chip experiment with the program hope you can help, including Happy Valley decimal significant organ SCM keyboard, using the 89C52 microcontroller button to play music microcontroller. On the keyb
8b10b_encdec
- There are four VHDL modules in the 8b10b_encdec project:: • 8b10b_enc.vhd • 8b10b_dec.vhd • enc_8b10b_TB.vhd • encdec_8b10b_TB.vhd-There are four VHDL modules in the 8b10b_encdec project:: • 8b10b_enc.vhd •
report
- vhdl code for basic gates, adders, subtractors , MUX and Demux
4-bit-adders
- four bit adders vhdl code
COMPARATORS
- comparator vhdl code
Decoders
- decoder(3:8) vhdl code
Priority-encoder
- priority encoders(3:8)(2:4)
lcdSync-1v0---Fully-functional-
- Quartus II SOPC lcd sync component with avalon streaming sink interface
fifo
- 异步FIFO源代码，由模块调用自动生成，不包含测试向量。-Asynchronous FIFO source code automatically generated by the module calls, does not contain the testbench.