资源列表
4-5
- 四舍五入判别电路，其输入为8421BCD码，要求当输大于或等于5时，判别电路输出为1，反之为0。-Four to five homes in judging circuit, the input to the 8421BCD code, when the distance is greater than or equal to 5, judging circuit outputs of 1, instead of 0.
verilog
- 矩阵键盘未消抖 用verilog语言编写，文件简介明了。容易看都和修改。-Matrix not away with verilog keyboard shake language, file introduction and clear. Easy to see all and modification.
FPGA-digital-clock-design
- 这是基于FPGA的多功能数字时钟设计。是一篇论文，看看吧。-This is the design of FPGA-based multi-function digital clock. A paper, look at it.
2
- VHDL百位计数器，实现计数功能，适合初学者学习-VHDL one hundred-bit counter counting function, suitable for beginners to learn
testbench(xilinx)
- Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计-The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the wa
4-_add
- 4 级流水方式的8 位全加器 vhdl 语音那描述-The level 4 water way QuanJia 8 bits for speech that described VHDL
4-a-string-and-converter
- 4 位串并转换器 vhdl语言 描述-4 a string and converter VHDL language describe
4-x-4-on-time-multiplier--table
- 4×4 查找表乘法器 vhdl 语言描述-4 x 4 on time-multiplier look-up table VHDL language describe
7-4-linear-space-time-block-codes-
- 7-4线性分组码编码器 vhdl描述-7-4 linear space-time block codes encoder vhdl derect
Eight-parallel-adder
- 8 位并行加法器 vhdl 语言描述-Eight parallel adder
Eight-parallel-by-skulls
- 8 位并行乘法器 vhdl语言描述-Eight parallel by skulls
jiaotongdeng11
- 交通灯设计方案 基于VHDL的红绿黄交通灯控制系统-Traffic light design Based on the VHDL red green and yellow traffic light control system