资源列表
seg71
- ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０--7 实验的目的是向用户介绍多个数码管动态显示的方法。 动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。-7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to th
all_cpu_scheduling
- the program gives cpu scheduling implementation
Yeni_klasr
- 8 bit Insruction register
ALU
- VHDL code for 3 bit ALU
MUX
- VHDL code for MUltiplexer
OR
- VHDL code for OR gate
frediv
- 1:1占空比的分频器的VHDL实现，包括奇数和偶数分频。-1:1 duty cycle of the divider of the VHDL implementation, including the odd and even frequency.
FFT
- FFT 高速傅立叶变换的VHDL源代码 可以综合。-FFT fast Fourier transform of the VHDL source code can be integrated.
UART2
- 串口UART描述，一经通过仿真并硬件实现。-Serial UART descr iption, once the simulation and hardware implementation.
VHDL10455361
- 一本很好的vhdl入门书籍《vhdl入门与应用》-A good introductory books vhdl " vhdl Introduction and Application"
sdram_initializer
- sdram模块控制功能，读取nop的sdram的机器- This module takes care of write, read and NOP state machine of SDRAM controller
testbench
- 视频转换测试程序，实现在芯片上进行视频加载-Video conversion test program