资源列表
perjoko_ting_ting
- Simple Microprocessor built with XILINX ISE
vote
- A project that count vote
processor
- The purpose of this project is to design a simple Processor Unit
addernew
- generate ripple carry adder
DE2_UserManual
- DE2使用手册，介绍DE2的所有组成元件，使用方法，还有相应的实例。-DE2 User Manual, describes all the components DE2 components, using the method, there is a corresponding instance.
LIP1733CORE_system_vbus_arbiter
- Verilog V Bus arbiter module
LIP1731CORE_system_gbus_arbiter
- Verilog system G bus arbiter module
TheVerilogHardwareDescriptionLanguage
- 国外的一本verilog方面的书籍，挺经典的。大家有兴趣的可以读一读，读原著的感觉很不一样，可以学到很多东西-Abroad, a verilog books, very classic. We are interested can read, Du Yuanzhu feel very different, you can learn a lot
huaweitongbudianlusheji
- 华为同步电路设计规范，里面有很多经验的东西，值得学习一下-Huawei synchronous circuit design, there are a lot of experience of things, it is worth learning about
Newnes_Design_Recipes_for_FPGAs
- This book is designed to be a desktop reference for engineers, students and researchers who use Field Programmable Gate Arrays(FPGA) as their hardware platform of choice.
quartusHH
- 基于Quartus II的EDA时钟模块-Quartus II EDA based on the clock module
CRC
- 循环冗余校验(CRC)模块设计 循环冗余校验(CRC)模块设计-Cyclic Redundancy Check (CRC) module design cyclic redundancy check (CRC) module design cyclic redundancy check (CRC) module design