资源列表
ddr2_demo
- lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
four-decimal-frequency--meter
- 基于VHDL语言设计实现的4位十进制的频率计及其在试验箱上的管脚连接-Based on VHDL language design of the realization of the four decimal frequency meter
The-traffic-lights--design
- 基于VHDL语言实现的交通灯控制电路的设计及其仿真-Based on VHDL language implementation of traffic light control circuit design and its simulation
Led-Display-
- 基于VHDL语言实现的七段数码显示译码器设计及其仿真-Based on VHDL language implementation of these seven digital display decoder design and simulation
frequency-divider
- 基于VHDL语言实现的数控分频器的设计及其仿真-Based on the numerical control language realization VHDL prescaler design and its simulation
adding-counter-
- 基于VHDL语言实现的 4位十进制频率计的设计及其仿真-Based on VHDL language implementation of four decimal frequency meter design and its simulation
m60BCD
- 异步清零多位计数器，应用verilog编程v-counter verilog configuration
elevmain1
- this is code fro elevator in vhdl
dianzizhong
- 用FPGA实现多功能电子钟的全部程序，包括亮度调整，时间日期现实与调整，闹钟和秒表-FPGA implementation of multi-function electronic clock procedures, including brightness adjustment, the reality and adjustment of the time and date, alarm clock and stopwatch
RS485
- /DM430-L型开发板RS485通信实验，通过开发板与电脑进行数据通信，485接在UART1上-/ DM430-L-type development board RS485 communication experiment, through the development board and computer data communications, 485 connection of the UART1
i2c_fsm.v
- This a verilog module which describes a i2c slave fsm with one-hot encode.-This is a verilog module which describes a i2c slave fsm with one-hot encode.
MyTimer
- 电子表功能描述 电子表共有5种功能：功能1为数字钟；功能2为数字跑表；功能3为调时；功能4为闹钟设置；功能5为日期设置。除调时功能以外，电子表处于其他功能状态下时并不影响数字钟的运行。使用数字钟功能时，还可以通过按键快速查看当前的闹钟设置时多功能间和当前日期。该电子表利用EDA实验平台的扬声器整点报时和定时报时，设置3个按键分别作为功能键和调整键。 -Functional descr iption of electronic clock： Electronic clock has a