资源列表
scr_20
- 完成20位并行数据的伪随机序列扰码，配合解码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 data-parallel pseudo-random sequence scrambling code with the decoding part, improve the SNR of the digital channel. Through integrated simulation, and run specific
descr_20
- 完成20位并行数据的伪随机序列解码，配合扰码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 pseudo-random sequence of parallel data decoding, with part of the scrambling code, and to improve the SNR of the digital channel. Through integrated simulation, an
complex_givens
- 基于cordic算法的givens变换实现矩阵QR分解-Transform matrix QR decomposition based on the givens of cordic algorithm
verilog-codes
- bit segmentation in wide division code multiple ace-bit segmentation in wide division code multiple acess
LCD_CALENDER
- 在12232液晶屏上显示当前的日期、时间及星期。按键A为日期、时间和星期 * * 切换按键-12232 LCD screen displays the current date, time and day of the week. A key date, time and day of the week* Switch button
Led7Seg
- LED 7 control source for 8051
Micron
- FPGA实现的NandFlash控制器（带ECC）文档+源代码-FPGA NandFlash controller (with ECC) document+ source code
VERILOG
- verilog的基础知识与编程基础，Verilog HDL 练习题-verilog basic knowledge of programming basics and Verilog HDL Exercise
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
sdram_controller
- SDRAM Controller Source Code
DE2_115_PS2_DEMO
- DE2-115开发板上的PS2针口程序，VHDL语言开发，QT2环境下可调式-PS2 pin port program the DE2-115 development board, VHDL language development, QT1 environment adjustable
DE2_115_NIOS_DEVICE_LED
- 基于NIOS开发环境下的LED灯综合程序，搭配使用QT2，开饭板为DE2-115-LED lights integrated program based on the NIOS development environment with QT1 dinner plate for the DE2-115