资源列表
vga_256
- 用FPGA控制VGA的Verilog程序，内附详细注释，已在CRT显示器上验证通过，希望对大家有用-FPGA VGA Verilog CRT
filter
- 设计一个16阶的低通FIR滤波器，对模拟信号的采样频率Fs为48KHz，要求信号的截止频率Fc=10.8kHz，输入序列位宽为9位（最高位为符号位）。-The FIR number filter example, designs a 16 ranks of low the FIR filter is a 48 khzs to the sample frequency Fs that imitates signal and request the closing of signal the fre
FSKPSK
- 本方案需要设计有100个单元的查找表，其中每个单元分别保存100个正弦波采样的对应样值。-This project needs to design to have checking of 100 unitses to seek form, among them, each unit keeps 100 sine wave samples respectively of to be worth in response to the kind.
Nios
- 利用Quartus II实现基于Nios的CPU软核设计实现。包括基本原理和实现代码。-Make use of Quartus II realization to design a realization according to the Nios CPU soft pit.Include basic principle and carry out a code.
PCM
- 本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。-This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL
dma_c2h_tutorial
- A C-code example for altera C-to-Hardware (C2H) conversion.
pit8253
- this is a code of 8253 programme interval timer in verilog
SEG7
- ALTERA公司DE2开发板的数码管驱动程序，包含引脚配置文件-ALTERA DE2 board digital driver contains the pin configuration files
83
- 基于FPGA的83优先编码器源代码，赛林思比赛专用-Based on FPGA 83 priority encoder the source code, and the "special LinSi game
jushuqi
- 基于FPGA的计数器器源代码，赛林思比赛专用-Based on FPGA counter is the source code, and the "special LinSi game
shumaguan
- 基于FPGA的动态数码管源代码，赛林思比赛专用-Based on FPGA dynamic digital tube the source code, and the "special LinSi game
wendu
- 基于FPGA的温度源代码，赛林思比赛专用-Based on FPGA temperature the source code, and the "special LinSi game