资源列表
prjadd
- vhdl计数器，在quartus81下调试通过-vhdl counter code. the code is passed with quartus81
New-Microsoft-Word-Document
- general code for counter
Copy-of-New-Microsoft-Word-Document
- pn-random code generator
Copy-(2)-of-New-Microsoft-Word-Document
- pn random code gerator fast
vhdllcd
- vhdllcd清零模块,实现LCD清屏归零相关功能-vhdl lcd
shizhong
- vhdl电子时钟（24小时制，时、分、秒）描述-VHDL electronic clock (24 hours to make, points seconds) descr iption
afifo
- verilog HDL fifo , verilog HDL fifo , -verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,verilog HDL fifo ,
VHDLfenpin
- VHDL整数、小数、分数、偶数、奇数、非50 分频器设计-VHDL integer decimal points even odd number not 50 prescaler design
pid_controler
- pid controller to give your experieces that builds your controller in your system
Diminishing-points-frequency
- 外接50M晶振，可分频为20、10、5、1KHz的占空比为50 的递减分频-External 50 M crystals, can divide frequency for 20, 10, 5, 1 KHz accounted for more than 50 of the empty diminishing points frequency
pwm
- 很详细的pwm控制电机内容，可调节占空比，调节精度可在程序中更改-Detailed pwm control motor, adjustable duty cycle, the regulation accuracy can be changed in the program
LCD12864
- 用verlog写的lcd12864显示汉字程序，测试效果不错-Written by verlog lcd12864 display Chinese characters procedures, test well