资源列表
A-New-Reversible-Design-of-BCD-Adder
- This a good implementation of reversible adder-This is a good implementation of reversible adder
code1
- Timing signal files verilog coding
running_light_schamatic_
- circuit diagramm is lunning light(led) with ic cd 4017 decade counter and -circuit diagramm is lunning light(led) with ic cd 4017 decade counter and 555
decoder
- decoder code in verilog/vhdl language
enc
- Encoder vhdl code basic implementation
vhdl_codes
- D-flip flop vhdl implement code
state
- state detection vhdl code implement
TP
- spice simulation file for analog ckt
FPGACPLD
- 描述FPGA与CPLD的区别，用于为初学者提供fpga与cpld的认识学习-Describe the difference between FPGA and CPLD, fpga and cpld understanding of learning for beginners
61EDA_H593
- 基于Spartan-3e的数码管显示时钟程序的设计(整个流程讲解详细)-Spartan-3e-based digital tube display clock program (the entire process to explain in detail)
spdl
- 射频电路测试原理典型射频芯片测试介绍与 测量仪器的程控(GPIB)-Typical radio frequency chip testing of RF circuit test principle introduced and Program-controlled measuring instruments (GPIB)
DS18B20
- Quartus 9.0 ，VHDL语言写的ds18b20 温度测量，1602液晶显示，还有报警功能，开发板用的是EP1C12F3234C8。-Quartus 9, VHDL language to write the DS18B20temperature measurement,1602 liquid crystal display, and the alarm function, development board is used in EP1C12F3234C8