资源列表
lcd1602
- Altera FPGA驱动lcd1602的程序，Verilog代码-Altera FPGA driver lcd1602 procedures, Verilog code
qiduanxianshiyima
- 利用译码程序在FPGA/CPLD中实现16进制数的译码显示.通过EDA原理图设计方法利用prim库中7448芯片进行7段译码显示-Using decode program FPGA/CPLD realized in hexadecimal number decoding display. Through the EDA principle diagram design method using the prim library 7448 chips for 7 period of decodin
vhdlbasicexamples
- VHDL 基础实例 范围广泛 非常值得学习-VHDL is based on a wide range of examples worth learning
Twobits-Adder
- Two bits Adder, this code allows add two bits variables using switches of FPGA, the result is shown in seven segments display. Include seven segments decoder module. The program was verified using BASYS 2 FPGA.
IPCORE_megadecryp
- IPCORE_megadecryp用于解密IPcore
homework1
- 清华大学微电子所研一的IC设计与方法第一次作业，由张春老师主讲。-Tsinghua University
5_ADC_Lab
- altear max10 adc demo，实验使用了2个adc，最大支持18路adc-altear max 10 demo with 2 adc， max support 18 channel adc
pc104vhdl_change
- PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程-PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:
verilog实现sata2传输协议
- 基于verilog实现sata传输协议以及接口操作功能。
attachments_2011_06_01
- hi........please find the attachment if ne-hi........please find the attachment if needed
codes-on-lcd
- for lcd code animated
50846288C
- verilog 硬件编程实现bpsk调制-verilog hardware, programming bpsk Modulation