资源列表
vgaclock.rar
- vga显示的数字时钟,用mif文件实现，用以大家学习交流,vga display digital clock, with the realization of mif file for them to learn from the exchange of
fenpin
- FPGA分频通用程序，使用时修改一个参数即可，使用modelsim开发环境-Frequency FPGA procedures, when used to modify a parameter, use the Modelsim development environment
zi-dong-shou-yin-liao-ji-
- 自动售出饮料机系统。该饮料机有五种饮料出售，其价钱分别为1元、1.5元、2元、2.5元和3元；系统可接受五种钱币类型，分别为硬币5角、硬币1元、纸币1元、纸币5元和纸币10元；基本要求：第一，每次可以购置一瓶饮料；第二，每次购置饮料可以接受多次钱币的投入；第三，可以找钱；-Automatic beverage machine systems sold. Five drinks in the beverage machine sale, its price is 1 yuan, 1.5 yuan,
100Examples[1`20]
- VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months
PWM
- pwm小程序 可以用于调节电压，输出不同的占空比的PWM波形-the pwm applet can be used to adjust the voltage, the output duty cycle of the PWM waveform
fir filter vhdl code
- FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
filter_VHDL
- FIR filter design using VHDL for 32 bit signed coefficientand 32 bit input and decimation is 4 and its working good
ep2c35_3.8_full_add
- 这个程序用verilog硬件语言编写。用来在FPGA内实现全加器。并且可以将输出显示在外部LED灯上等。-this program is writen by verilog HDL.it is the full adder for FPGA.users can read the result from the LEDs.
up_test
- 基于vhdl语言的源代码，用于检测信号的上升沿，多用于同步时钟-Vhdl source code based on the language used to detect the rising edge, used for synchronous clock
shuzipaobiao
- 数字跑表 已经验证 请放心下载 基于fpga-Digital stopwatch has been verified, please rest assured download
verilogled7
- 基于epm240的学习文件，这个程序是关于七段数码管的学习程序-Learning based epm240 files, this program is about seven-segment of the learning process
zhuangtai
- 本程序实现了报文功能，在通信传输中经常会用到，使用芯片为xilinx，verilog语言编写-This program implements packets, in the communication transmission is often used, the use of chip xilinx, verilog language