资源列表
VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
DDS
- 基于FPGA的DDS正弦信号设计，文件中有源代码(Design of DDS based on FPGA)
fullAdder_4bit
- This is fullAdder_4bit with testbench.
VHDL-SPI-Module
- This an small program which write in VHDL it is mainly used to read/write serial data by SPI model -This is an small program which write in VHDL it is mainly used to read/write serial data by SPI model
_2_sw_led
- verilog实例2 sw_led 使用拨动开关控制LED亮灭 （1）源文件 sw_led.v （2）管脚分配 pins list.txt -2 sw_led 使用拨动开关控制LED亮灭 （1）源文件 sw_led.v （2）管脚分配 pins list.txt
_2_sw_led
- 开关控制led灯，verilog语言代码，对初学者有很大帮助-Switch led light, verilog language code, very helpful for beginners
QuartusII9.0crack
- quartus 2 v.9.0 program
DE2_i2sound-g5
- 通过de2板上的wm8731，42阶音量可调，mic和dac同时输出。-By de2 board wm8731, 42 stage adjustable volume, mic and dac output simultaneously.
3-3-median-filter
- verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
Verilog_pingpang
- 其实乒乓操作用面积换速度，本文件是用verilog实现乒乓操作-In fact, with an area for ping-pong operation speed, this document is to achieve pong operation verilog
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)
Oscilloscope_V1.0
- XAPP Oscillscope VHDL code