资源列表
wendu_convert
- 完成一个摄氏温度（的整数）转化为华氏温度的电路，关系如下： F＝C*9/5+32-A Celsius temperature to complete the (integer) into circuit Fahrenheit, relations are as follows: F = C*9/5+32
CPLD_LCD
- 用verilog编写的1602显示屏的程序，通用性较强，测试平台是DE0-Written in verilog 1602 Display of the program, versatility is strong, the test platform is DE0
hmjieshou
- 通过使用fpga的串口来实现汉明码的接收并可以成功进行解码-Hamming receiver using fpga serial port and can successfully decode
xapp622.zip
- 644 MHz SDR LVDS 发射器/接收器(verilog and doc),644-MHz SDR LVDS Transmitter/Receiver
SPI_on-quartus
- spi master code for fpga quartus altera
shumaguan
- 四个数码管静态显示，且让数码管循环显示0到F-Four digital tube static display and digital control loop 0 to F
verilogdesign
- 包含大量得实例,用于学习verilog语言.
CatchCadCoordinate
- 捕获CAD中鼠表的位置坐标,用VS STADIO 开发 -catch mice CAD table position coordinates with the development of VS STADIO
GTX_AURORA_MAIN
- 将数据从板卡网口(Ethernet Mac)经过fifo发至GTX高速串行口 ISE -The data from the network interface card (Ethernet Mac) through fifo GTX sent to high-speed serial port ISE
kpjsj
- 次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序
FPGA_SPI_master
- master spi code for quartus
textiowrite
- quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。-Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.